Analysis of reliability for fault tolerant design in NANO CMOS logic circuit. Experimental and Theoretical NANOTECHNOLOGY, [S. l.], v. 2, n. 1, p. 43–58, 2018. DOI: 10.56053/2.1.43. Disponível em: https://etnano.com/index.php/journal/article/view/98.. Acesso em: 16 oct. 2024.